1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits, and more specifically to a method of protecting underlying dielectric and metal layers during wet etch by depositing silicon nitride layers.
2. Description of the Prior Art
In semiconductor integrated circuits, formation of interconnect layers is important to the proper operation of these devices. Interconnect signal lines make contact to lower conductive layers of the integrated circuit through vias in an insulating layer. For best operation of the device, the lower conductive layers should not be damaged during formation of the contact via.
Various interlevel dielectric layers are deposited on the integrated circuit during formation of the device. These layers separate the conductive layers from each other. One way to form contact vias through these insulating layers is by a process which utilizes both an isotropic wet etch and an anisotropic plasma etch. A wet etch is performed by exposing the integrated circuit to liquid chemicals, such as hydrogen fluoride. After a via has been opened part way through the insulating layer, an anisotropic etch is performed to expose the underlying conductive layer.
During a wet etch, undesirable voids, defects or stressed regions in a dielectric layer allow the chemicals to travel through the dielectric layers to the underlying conductive layers. This causes some of the conductive material to be etched away, leaving spots where conductive material in a conductive layer is missing. An integrated circuit with missing conductive material is unreliable, and possibly non-functional.
An approach presently used to minimize the possibility of conductive material being etched away is to reduce the period of time allocated for wet etching. This minimizes the likelihood that the underlying conductor will be damaged. However, decreasing the wet etch time also decreases the metal step coverage improvement realized by using a partial wet etch.
The problems caused during a wet etch by chemicals etching material not intended to be removed is not limited to conductive interconnect layers. Mouse bites in die boundaries and holes in bond pads are also attributed to the attack of metal during the formation of vias by wet etching.
It would be desirable to provide a technique to incorporate a layer of material in the interlevel dielectric layers which would act as a wet etch stop during via formation.